Texas Instruments /MSP432P401Y /FLCTL_A /FLCTL_PRG_CTLSTAT

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Interpret as FLCTL_PRG_CTLSTAT

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ENABLE_0)ENABLE 0 (MODE_0)MODE 0 (VER_PRE_0)VER_PRE 0 (VER_PST_0)VER_PST 0 (STATUS_0)STATUS 0 (BNK_ACT_0)BNK_ACT

VER_PST=VER_PST_0, BNK_ACT=BNK_ACT_0, STATUS=STATUS_0, MODE=MODE_0, VER_PRE=VER_PRE_0, ENABLE=ENABLE_0

Description

Program Control and Status Register

Fields

ENABLE

Master control for all word program operations

0 (ENABLE_0): Word program operation disabled

1 (ENABLE_1): Word program operation enabled

MODE

Write mode

0 (MODE_0): Write immediate mode. Starts program operation immediately on each write to the Flash

1 (MODE_1): Full word write mode. Flash controller collates data over multiple writes to compose the full 128bit word before initiating the program operation

VER_PRE

Controls automatic pre program verify operations

0 (VER_PRE_0): No pre program verification

1 (VER_PRE_1): Pre verify feature automatically invoked for each write operation (irrespective of the mode)

VER_PST

Controls automatic post program verify operations

0 (VER_PST_0): No post program verification

1 (VER_PST_1): Post verify feature automatically invoked for each write operation (irrespective of the mode)

STATUS

Status of program operations in the Flash memory

0 (STATUS_0): Idle (no program operation currently active)

1 (STATUS_1): Single word program operation triggered, but pending

2 (STATUS_2): Single word program in progress

BNK_ACT

Bank active

0 (BNK_ACT_0): Word in Bank0 being programmed

1 (BNK_ACT_1): Word in Bank1 being programmed

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